The 74HC165; 74HCT165 are 8-bit serial or parallel-in/serial-out shift registers. The device
features a serial data input (DS), eight parallel data inputs (D0 to D7) and two complementary
serial outputs (Q7 and Q7). When the parallel load input (PL) is LOW the data from D0 to D7 is
loaded into the shift register asynchronously. When PL is HIGH data enters the register serially at
DS. When the clock enable input (CE) is LOW data is shifted on the LOW-to-HIGH transitions of
the CP input. A HIGH on CE will disable the CP input. Inputs are overvoltage tolerant to 15 V. This
enables the device to be used in HIGH-to-LOW level shifting applications.
Features and benefits
• Wide supply voltage range from 2.0 V to 6.0 V
• CMOS low power dissipation
• High noise immunity
• Latch-up performance exceeds 100 mA per JESD 78 Class II Level B
• Asynchronous 8-bit parallel load
• Synchronous serial input
• Input levels:
• For 74HC165: CMOS level
• For 74HCT165: TTL level
• Complies with JEDEC standards:
• JESD8C (2.7 V to 3.6 V)
• JESD7A (2.0 V to 6.0 V)
• ESD protection:
• HBM: ANSI/ESDA/JEDEC JS-001 class 2 exceeds 2000 V
• CDM: ANSI/ESDA/JEDEC JS-002 class C3 exceeds 1000 V
• Multiple package options
• Specified from -40 °C to +85 °C and from -40 °C to +125 °C
Applications
• Parallel-to-serial data conversion
This 16-pin device features asynchronous parallel load (active LOW), rising-edge triggered clock input, and complementary/serial outputs. It includes 8 parallel data inputs (D0–D7), a serial data input (DS), clock enable (active LOW), ground (GND), and positive supply (VCC), supporting parallel-to-serial data conversion.